--
-- Component : w_mux
--
-- Generated by System Architect version v8.5_2.2 by w-hong on Apr 13, 97
--
-- sensitivity_attr :: 'transaction

-- this is a latched mux, so that DOut will be
-- valid at and after 2 ns

ARCHITECTURE spec OF w_mux IS
	signal result : mips_word;

BEGIN

   -------------------------------------------------------------------
   vhdl_w_mux : PROCESS (CLK)
   -------------------------------------------------------------------
   BEGIN
	if (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0') then
		case selW_M is
		when "00" =>
			result <= ALU_M;
		when "01" =>
			result <= PC_M;
		when "10" =>
			result <= MOut_M;
		when others =>
			result <= (OTHERS => 'X');
		end case;
	end if;
   END PROCESS vhdl_w_mux ;

   DOut <= result after 2 ns;
END spec ;