--
-- Component : w_latch
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Apr 04, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF w_latch IS
	signal RW : mips_register;
	signal I : mips_word;
	signal RegW : std_logic;

BEGIN
   -------------------------------------------------------------------
   vhdl_w_latch : PROCESS (CLK, RESET_L)
   -------------------------------------------------------------------
   BEGIN
	if (RESET_L = '0') then
		RW <= (OTHERS => '0');
		I <= (OTHERS => '0');
		RegW <= '0';
	elsif (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0') then
		RW <= RW_M;
		I <= I_M;
		RegW <= RegW_M;
	end if;
   END PROCESS vhdl_w_latch ;

   RW_W <= RW after 2 ns;
   I_W <= I after 2 ns;
   RegW_W <= RegW after 2 ns;
END spec ;