--
-- Component : m_latch
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Apr 04, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF m_latch IS
	signal oldRW : mips_register;
	signal oldI : mips_word;
	signal oldPC : mips_word;
	signal oldROut : mips_word;
	signal oldALU : mips_word;
	signal MMRead : std_logic;
	signal MMWrite : std_logic;
	signal RegW : std_logic;
	signal selW : mips_mux_2;

BEGIN
   -------------------------------------------------------------------
   vhdl_m_latch : PROCESS (CLK, RESET_L)
   -------------------------------------------------------------------
   BEGIN
	if (RESET_L = '0') then
		oldRW <= (OTHERS => '0');
		oldI <= (OTHERS => '0');
		oldPC <= (OTHERS => '0');
		oldROut <= (OTHERS => '0');
		oldALU <= (OTHERS => '0');
		MMRead <= '0';
		MMWrite <= '0';
		RegW <= '0';
		selW <= (OTHERS => '0');
	elsif (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0'
               AND MemStall_H = '0') then
		oldRW <= RW_X;
		oldI <= I_X;
		oldPC <= PC_X;
		oldROut <= ROut_X;
		oldALU <= ALU_X;
		MMRead <= C_X(0);
		MMWrite <= C_X(1);
		RegW <= C_X(2);
		selW <= C_X(4 downto 3);			
	end if;
   END PROCESS vhdl_m_latch ;

   RW_M <= oldRW after 2 ns;
   I_M <= oldI after 2 ns;
   PC_M <= oldPC after 2 ns;
   ROut_M <= oldROut after 2 ns;
   ALU_M <= oldALU after 2 ns;
   MMREAD_H <= MMRead after 2 ns;
   MMWRITE_H <= MMWrite after 2 ns;
   RegW_M <= RegW after 2 ns;
   selW_M <= selW after 2 ns;
END spec ;