--
-- Component : pc
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 20, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF pc IS
	signal prePC : mips_word;
	signal start : std_logic;
BEGIN
   -------------------------------------------------------------------
   vhdl_pc : PROCESS (CLK, RESET_L)
   -------------------------------------------------------------------
   BEGIN
	if (RESET_L = '0') then
		prePC <= (OTHERS => '0');
	elsif (RESET_L'EVENT AND RESET_L = '1' AND
		RESET_L'LAST_VALUE = '0') then
		start <= '1';
	elsif (CLK'EVENT AND CLK = '1' AND MemStall_H = '0'
		AND CLK'LAST_VALUE = '0' AND Stall ='0') then
		if (start = '1') then
			start <= '0';
			prePC <= (OTHERS => '0');
		else
			prePC <= PCIn;
		end if;
	end if;
   END PROCESS vhdl_pc ;

   PC_F <= prePC after 2 ns;
END spec ;