--
-- Component : x_latch
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 21, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF x_latch IS
	signal RW : mips_register;
	signal I : mips_word;
	signal PC : mips_word;
	signal C : mips_ctrl_x;
	signal Imm : mips_word;
	signal ROut1 : mips_word;
	signal ROut2 : mips_word;
	signal ShAmt : mips_word;
BEGIN
   -------------------------------------------------------------------
   vhdl_x_latch : PROCESS (CLK, RESET_L)
   -------------------------------------------------------------------
   BEGIN
	if (RESET_L = '0') then
		RW <= (OTHERS => '0');
		I <= (OTHERS => '0');
		PC <= (OTHERS => '0');
		C <= (OTHERS => '0');
		Imm <= (OTHERS => '0');
		ROut1 <= (OTHERS => '0');
		ROut2 <= (OTHERS => '0');
		ShAmt <= (OTHERS => '0');
	elsif (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0' AND
	       MEMSTALL_H = '0') then
		RW <= RW_D;
		I <= I_D;
		PC <= PC_4;
		C <= C_D;
		Imm <= Imm_D;
		ROut1 <= ROut1_D;
		ROut2 <= ROut2_D;
		ShAmt <= zero_extend(ShAmt_D, 32);
		if (Bubble = '1') then
			RW <= (OTHERS => '0');
			I <= (OTHERS => '0');
			PC <= (OTHERS => '0');
			C <= (OTHERS => '0');
			Imm <= (OTHERS => '0');
			ROut1 <= (OTHERS => '0');
			ROut2 <= (OTHERS => '0');
			ShAmt <= (OTHERS => '0');
		end if;
	end if;

   END PROCESS vhdl_x_latch ;
   RW_X <= RW after 2 ns;
   I_X_i <= I after 2 ns;
   PC_X <= PC after 2 ns;
   C_X_i <= C after 2 ns;
   Imm_X <= Imm after 2 ns;
   ROut1_X <= ROut1 after 2 ns;
   ROut2_X <= ROut2 after 2 ns;
   ShAmt_X <= ShAmt after 2 ns;

END spec ;