--
-- Component : forward_unit
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Apr 03, 97
--
-- sensitivity_attr :: 'transaction

-- alu selection and forwarding control
-- in order to keep the clock cycle low, this runs in parallel
-- with the latch (during a rising edge), and will examine 
-- values from states before the new ones are latched

ARCHITECTURE spec OF forward_unit IS
	signal A : mips_mux_2;
	signal B : mips_mux_2;
	signal r : mips_mux_2;
BEGIN
   -------------------------------------------------------------------
   vhdl_forward_unit : PROCESS (CLK)
   -------------------------------------------------------------------
   BEGIN
	if (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0') then
		--by default use register values
		A <= "00";
		B <= "00";
		r <= "00";
	
		--check for forwarding
		if (RegW_M = '1' AND RW_M /= "00000") then
			if (RW_M = RS_D) then
				A <= "11";
			end if;	
			if (RW_M = RT_D) then
				B <= "11";
				r <= "10";
			end if;
		end if;

		if (RegW_X = '1' AND RW_X /= "00000") then
			if (RW_X = RS_D) then
				A <= "10";
			end if;
			if	(RW_X = RT_D) then
				B <= "10";
				r <= "01";
			end if;
		end if;
	
		--check if shamt needed
		if(I_Type = "01") then
			A <= "01";
		end if;

		--check if immediate is needed
		if(I_Type = "10") then
			B <= "01";
		end if;
	end if;

   END PROCESS vhdl_forward_unit;
   selAA <= A after 2 ns;
   selAB <= B after 2 ns;
   selr <= r after 2 ns;

END spec ;