--
-- Component : alu
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 

-- This alu performs 32 bit addition, subtraction, logical or, logical and,
-- logical shifts and a set-on-less-than. 

ARCHITECTURE spec OF alu IS
BEGIN
   -------------------------------------------------------------------
   vhdl_alu : PROCESS (ALUOp, inA, inB)
   -------------------------------------------------------------------
	variable result : mips_word;
	variable temp1 : mips_word;
	variable temp2 : mips_word;
	variable sha : integer range 0 to 31;
   BEGIN
	case ALUOp is 
	when alu_ADD =>
		result := inA + inB;
 	when alu_SUB =>
		result := inA - inB;
	when alu_AND =>
		result := inA AND inB;
	when alu_OR  =>
		result := inA OR inB;
	when alu_SLL =>
		sha := to_integer(inA(4 downto 0),0);
		result := inB sll sha;
	when alu_SRL =>
		sha := to_integer(inA(4 downto 0),0);
		result := inB srl sha;
	when alu_SLT =>
	        temp1 := inA;
        	temp2 := inB;
		temp1(temp1'left) := not temp1(temp1'left);
        	temp2(temp2'left) := not temp2(temp2'left);
		if ( temp1 < temp2 ) then
			result := to_stdlogicvector(0,31) & '1';
        	else
          		result := to_stdlogicvector(0,32);
        	end if;
	when alu_LUI =>
		result := inB sll 16;
	when others =>
		result := (OTHERS => 'X');
	end case;
  
	ALU_X <= result after 9 ns;

   END PROCESS vhdl_alu ;
END spec ;