--
-- Component : rw_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 20, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF rw_mux IS
BEGIN
   -------------------------------------------------------------------
   vhdl_rw_mux : PROCESS (RD, RT_D, selRW)
   -------------------------------------------------------------------
	variable state : mips_register;
   BEGIN
	case selRW is
	when "00" =>
		state := RT_D;
	when "01" =>
		state := RD;
	when "10" =>
		state := to_stdlogicvector(31, 5);
	when others =>
		state := (OTHERS => 'X');
	end case;

	RW_D <= state after 2 ns;

   END PROCESS vhdl_rw_mux ;
END spec ;