--
-- Component : registers
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 20, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF registers IS
	signal clock_delayed : std_logic;
	type rammemory is array (31 downto 0) of mips_word;
	signal ram : rammemory;
	signal c_reg : mips_register;
	signal c_val : mips_word;       
BEGIN 

   -------------------------------------------------------------------
   delay_clock : PROCESS(CLK)
   -------------------------------------------------------------------
   -- need the delay of 2ns for DOut to be valid for the current instruction
   BEGIN
	clock_delayed <= CLK after 2 ns;
   end PROCESS delay_clock;

   -------------------------------------------------------------------
   vhdl_regfile_read : PROCESS (ram, RS_D, RT_D)
   -------------------------------------------------------------------
	variable raddr1 : integer range 0 to 31;
	variable raddr2 : integer range 0 to 31;
   begin
   -- Read regfile Process.
   -- convert addresses to integers to use as an index into the array.
	if (RS_D = c_reg) then
		ROut1_D <= c_val;
	else
		raddr1 := to_Integer("000" & RS_D,0);
		ROut1_D <= ram(raddr1) after 4 ns;
	end if;

	if (RT_D = c_reg) then
		ROut2_D <= c_val;
	else
		raddr2 := to_Integer("000" & RT_D,0);
		ROut2_D <= ram(raddr2) after 4 ns;
	end if;
   end process vhdl_regfile_read;

   -------------------------------------------------------------------
   vhdl_regfile_write: process(clock_delayed, RW_W, DOut, RegW_W)
   -------------------------------------------------------------------
	variable waddr : integer range 0 to 31;
   begin
   -- convert address to integer
	waddr := to_Integer("000" & RW_W,0);
	if (clock_delayed'event and clock_delayed = '1' and
	    clock_delayed'last_value = '0') then
		-- as specified in Patterson & Hennessy, a 
		-- register file may have a 'buffer' such
		-- that it may output the value it it currently
		-- writing. This avoids the need for third level
		-- bypassing. 
		c_reg <= RW_W;		-- register currently writing
		c_val <= DOut;		-- data value currently writing
		if (RegW_W = '1') then
			ram(waddr) <= DOut after 8 ns;
		end if;
	end if;

	ram(0) <= to_stdlogicvector(0,32);

   end process vhdl_regfile_write;
END spec ;