--
-- Component : d_latch
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 20, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF d_latch IS
	signal oldI : mips_word; 
	signal oldPC : mips_word;  
	signal oldPC_4: mips_word;
BEGIN
   -------------------------------------------------------------------
   vhdl_d_latch : PROCESS (CLK, RESET_L, Flush, Stall)
   -------------------------------------------------------------------
   BEGIN
	if (RESET_L = '0') then
		oldI <= (OTHERS => '0');
		oldPC <= (OTHERS => '0');
		oldPC_4 <= (OTHERS => '0');
	elsif (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0' AND
	       Stall = '0' AND MemStall_H = '0') then
		if (Flush = '1') then
  			oldI <= (OTHERS => '0');
			oldPC <= (OTHERS => '0');
			oldPC_4 <= (OTHERS => '0');
		else
			oldI <= I_F;
			oldPC <= PC_F;
			oldPC_4 <= NextPC;
		end if;
	end if;

   END PROCESS vhdl_d_latch ;

   I_D_i <= oldI after 2 ns;
   PC_D <= oldPC after 2 ns;
   PC_4 <= oldPC_4 after 2 ns;
END spec ;