--
-- Component : control_unit
--
-- Generated by System Architect version v8.5_2.2 by w-hong on Apr 13, 97
--
-- sensitivity_attr :: 'transaction
-- Source views :-
-- $ECE_312_MP3/mips_types/types
--

ARCHITECTURE spec OF control_unit IS
BEGIN
   -------------------------------------------------------------------
   vhdl_control_unit : PROCESS (Op, Func)
   -------------------------------------------------------------------
	variable R_Type : mips_type;
	variable R_ExType : std_logic;
	variable R_selW : mips_mux_2;
	variable R_RegW : std_logic;
	variable R_MMREAD : std_logic;
	variable R_MMWRITE : std_logic;
	variable R_C : mips_ctrl_x;
	variable R_selRW : mips_mux_2;
   BEGIN
	R_Type := "00";
	if (Op = rType) then
		if (Func = cSLL OR Func = cSRL) then
			R_Type := "01";
		end if; 
	elsif (Op = oADDI OR Op = oANDI OR Op = oLUI OR Op = oORI OR
	       Op = oSLTI OR Op = oLW OR Op = oSW) then
		R_Type := "10";
	end if;

	R_ExType := '1';
	if (Op = oANDI OR Op = oORI) then
		R_ExType := '0';
	end if;

	R_RegW := '1';
	if (Op = oBEQ OR Op = oBNE OR Op = oJ OR Op = oSW) then
		R_RegW := '0';
	end if;

	R_MMREAD := '0';
	R_MMWRITE := '0';
	if (Op = oSW) then
		R_MMWRITE := '1';
	elsif (Op = oLW) then
		R_MMREAD := '1';
	end if;

	R_selW := "00";
	if (Op = oJAL) then
		R_selW := "01";
	elsif (Op = oLW) then
		R_selW := "10";
	end if;

	R_C := R_selW & R_RegW & R_MMWRITE & R_MMREAD;

	R_selRW := "00";
	if (Op = rType) then
		R_selRW := "01";
	elsif (Op = oJAL) then
		R_selRW := "10";
	end if;

	I_Type <= R_Type after 2 ns;
	ExType <= R_ExType after 2 ns;
	C_D <= R_C after 2 ns;
	selRW <= R_selRW after 2 ns;

   END PROCESS vhdl_control_unit ;
END spec ;