--
-- Component : comp
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Mar 20, 97
--
-- sensitivity_attr :: 'transaction

ARCHITECTURE spec OF comp IS
BEGIN
   -------------------------------------------------------------------
   vhdl_comp : PROCESS (B1, B2)
   -------------------------------------------------------------------
	variable result : std_logic;
   BEGIN
	if (B1 = B2) then
		result := '1';
	else
		result := '0';
	end if;

	Eq <= result after 2 ns;

   END PROCESS vhdl_comp ;
END spec ;