--
-- Component : branch_forward
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Apr 03, 97
--
-- sensitivity_attr :: 'transaction

-- Controls data forwarding for branch resolution

ARCHITECTURE spec OF branch_forward IS
BEGIN

   -------------------------------------------------------------------
   vhdl_branch_forward : PROCESS (RS_D, RT_D, RW_X, RW_M, RW_W, MMREAD_H,
				  Op, Func, RegW_X, RegW_M, RegW_W)
   -------------------------------------------------------------------
	variable R_Stall  : std_logic;
	variable R_Bubble : std_logic;
	variable R_selBA  : mips_mux_2;
	variable R_selBB  : mips_mux_2;
   BEGIN		
	R_Stall := '0';
	R_Bubble := '0';
	R_selBA := "00";
	R_selBB := "00";

	if (RegW_W = '1') then
		if (RS_D = RW_W) then
			R_selBA := "10";
		end if;
		if (RT_D = RW_W) then
			R_selBB := "10";
		end if;
	end if;

	if (RegW_M = '1') then
		if (RS_D = RW_M) then
			if (MMREAD_H = '1') then
				R_Stall := '1';
				R_Bubble := '1';			
			else
				R_selBA := "01";
			end if;
		end if;
		if (RT_D = RW_M) then
			if (MMREAD_H = '1') then
				R_Stall := '1';
				R_Bubble := '1';			
			else
				R_selBB := "01";
			end if;
		end if;
	end if;

	if (Op = oBNE OR Op = oBEQ OR (Op = rType AND Func = cJR)) then
   		if (RegW_X = '1') then
 			if (RS_D = RW_X OR RT_D = RW_X) then
				R_Stall := '1';
				R_Bubble := '1';
			end if;
		end if;
	end if;

	Stall <= R_Stall after 2 ns;
	Bubble <= R_Bubble after 2 ns;
	selBA <= R_selBA after 2 ns;
	selBB <= R_selBB after 2 ns;

   END PROCESS vhdl_branch_forward ;
END spec ;