--
-- Component : ext_data_mem
--
-- Generated by System Architect version v8.5_2.2 by w-hong on May 06, 97
--
-- sensitivity_attr :: 'transaction
-- Source views :-
-- $ECE_312_MP3/mips_types/types
--

ARCHITECTURE spec OF ext_data_mem IS
BEGIN

   -------------------------------------------------------------------
   vhdl_ext_data_mem : PROCESS (Address, MemRead, MemWrite, RESET_L, WBData)
   -------------------------------------------------------------------
	TYPE memory_array IS array (0 to 2048) of mips_word;
        VARIABLE mem : memory_array;
        VARIABLE int_address : integer;
        VARIABLE temp : string(1 to 10);
        VARIABLE temp_int : integer;
        VARIABLE MMREAD_L : std_logic;
        VARIABLE MMWRITE_L : std_logic;
   BEGIN
        int_address := to_integer('0' & Address(10 downto 0));

	if Reset_L = '0' then

-- Initialize Data Memory vectors

-- BEGIN DATA MEMORY VECTORS 

mem(0) := To_stdlogicvector(16#3C020000#, 32);
mem(4) := To_stdlogicvector(16#8C420180#, 32);
mem(8) := To_stdlogicvector(16#00000000#, 32);
mem(12) := To_stdlogicvector(16#00000000#, 32);
mem(16) := To_stdlogicvector(16#8C430000#, 32);
mem(20) := To_stdlogicvector(16#8C440004#, 32);
mem(24) := To_stdlogicvector(16#8C450008#, 32);
mem(28) := To_stdlogicvector(16#8C46000C#, 32);
mem(32) := To_stdlogicvector(16#8C470010#, 32);
mem(36) := To_stdlogicvector(16#8C480014#, 32);
mem(40) := To_stdlogicvector(16#8C490018#, 32);
mem(44) := To_stdlogicvector(16#8C4A001C#, 32);
mem(48) := To_stdlogicvector(16#8C4B0020#, 32);
mem(52) := To_stdlogicvector(16#8C4C0024#, 32);
mem(56) := To_stdlogicvector(16#8C4D0028#, 32);
mem(60) := To_stdlogicvector(16#8C4E002C#, 32);
mem(64) := To_stdlogicvector(16#8C4F0030#, 32);
mem(68) := To_stdlogicvector(16#8C500034#, 32);
mem(72) := To_stdlogicvector(16#8C510038#, 32);
mem(76) := To_stdlogicvector(16#8C52003C#, 32);
mem(80) := To_stdlogicvector(16#8C530030#, 32);
mem(84) := To_stdlogicvector(16#3C020000#, 32);
mem(88) := To_stdlogicvector(16#8C420184#, 32);
mem(92) := To_stdlogicvector(16#00000000#, 32);
mem(96) := To_stdlogicvector(16#00000000#, 32);
mem(100) := To_stdlogicvector(16#AC4B0000#, 32);
mem(104) := To_stdlogicvector(16#AC4C0004#, 32);
mem(108) := To_stdlogicvector(16#AC4D0008#, 32);
mem(112) := To_stdlogicvector(16#AC4E000C#, 32);
mem(116) := To_stdlogicvector(16#AC500014#, 32);
mem(120) := To_stdlogicvector(16#AC4F0010#, 32);
mem(124) := To_stdlogicvector(16#AC510018#, 32);
mem(128) := To_stdlogicvector(16#AC52001C#, 32);
mem(132) := To_stdlogicvector(16#3C160000#, 32);
mem(136) := To_stdlogicvector(16#8ED60400#, 32);
mem(140) := To_stdlogicvector(16#3C170000#, 32);
mem(144) := To_stdlogicvector(16#8EF70404#, 32);
mem(148) := To_stdlogicvector(16#8C5A0008#, 32);
mem(152) := To_stdlogicvector(16#8C580000#, 32);
mem(156) := To_stdlogicvector(16#8C590004#, 32);
mem(160) := To_stdlogicvector(16#8C5B000C#, 32);
mem(164) := To_stdlogicvector(16#3C010000#, 32);
mem(168) := To_stdlogicvector(16#AC230710#, 32);
mem(172) := To_stdlogicvector(16#3C010000#, 32);
mem(176) := To_stdlogicvector(16#AC240718#, 32);
mem(180) := To_stdlogicvector(16#8C580014#, 32);
mem(184) := To_stdlogicvector(16#8C590010#, 32);
mem(188) := To_stdlogicvector(16#8C5A0018#, 32);
mem(192) := To_stdlogicvector(16#8C5B001C#, 32);
mem(196) := To_stdlogicvector(16#3C1A5555#, 32);
mem(200) := To_stdlogicvector(16#3C050000#, 32);
mem(204) := To_stdlogicvector(16#8CA50188#, 32);
mem(208) := To_stdlogicvector(16#00000000#, 32);
mem(212) := To_stdlogicvector(16#035A5020#, 32);
mem(216) := To_stdlogicvector(16#03455822#, 32);
mem(220) := To_stdlogicvector(16#03456024#, 32);
mem(224) := To_stdlogicvector(16#03456825#, 32);
mem(228) := To_stdlogicvector(16#00057400#, 32);
mem(232) := To_stdlogicvector(16#00057B02#, 32);
mem(236) := To_stdlogicvector(16#31701F1F#, 32);
mem(240) := To_stdlogicvector(16#35713333#, 32);
mem(244) := To_stdlogicvector(16#21521234#, 32);
mem(248) := To_stdlogicvector(16#2173FFFC#, 32);
mem(252) := To_stdlogicvector(16#014BA02A#, 32);
mem(256) := To_stdlogicvector(16#016AA82A#, 32);
mem(260) := To_stdlogicvector(16#2816000A#, 32);
mem(264) := To_stdlogicvector(16#2957FFFF#, 32);
mem(268) := To_stdlogicvector(16#08000043#, 32);
mem(272) := To_stdlogicvector(16#00000000#, 32);
mem(276) := To_stdlogicvector(16#00000000#, 32);
mem(280) := To_stdlogicvector(16#00000000#, 32);
mem(284) := To_stdlogicvector(16#00000000#, 32);
mem(288) := To_stdlogicvector(16#00000000#, 32);
mem(292) := To_stdlogicvector(16#00000000#, 32);
mem(296) := To_stdlogicvector(16#00000000#, 32);

-- BEGIN DATA MEMORY VECTORS 
mem(384) := To_stdlogicvector(16#00000200#, 32);
mem(388) := To_stdlogicvector(16#00000500#, 32);
mem(392) := To_stdlogicvector(16#12345678#, 32);
mem(396) := To_stdlogicvector(16#00000000#, 32);
mem(400) := To_stdlogicvector(16#00000000#, 32);
mem(404) := To_stdlogicvector(16#00000000#, 32);
mem(408) := To_stdlogicvector(16#00000000#, 32);
mem(412) := To_stdlogicvector(16#00000000#, 32);
mem(512) := To_stdlogicvector(16#12345678#, 32);
mem(516) := To_stdlogicvector(16#ABCD1234#, 32);
mem(520) := To_stdlogicvector(16#00001111#, 32);
mem(524) := To_stdlogicvector(16#22223333#, 32);
mem(528) := To_stdlogicvector(16#44445555#, 32);
mem(532) := To_stdlogicvector(16#66667777#, 32);
mem(536) := To_stdlogicvector(16#88889999#, 32);
mem(540) := To_stdlogicvector(16#AAAABBBB#, 32);
mem(544) := To_stdlogicvector(16#CCCCDDDD#, 32);
mem(548) := To_stdlogicvector(16#EEEEFFFF#, 32);
mem(552) := To_stdlogicvector(16#12121212#, 32);
mem(556) := To_stdlogicvector(16#34343434#, 32);
mem(560) := To_stdlogicvector(16#56565656#, 32);
mem(564) := To_stdlogicvector(16#78787878#, 32);
mem(568) := To_stdlogicvector(16#89898989#, 32);
mem(572) := To_stdlogicvector(16#ABABABAB#, 32);
mem(576) := To_stdlogicvector(16#00000000#, 32);
mem(580) := To_stdlogicvector(16#00000000#, 32);
mem(584) := To_stdlogicvector(16#00000000#, 32);
mem(588) := To_stdlogicvector(16#00000000#, 32);
mem(592) := To_stdlogicvector(16#00000000#, 32);
mem(1024) := To_stdlogicvector(16#AABBCCDD#, 32);
mem(1028) := To_stdlogicvector(16#DDCCBBAA#, 32);
mem(1032) := To_stdlogicvector(16#11223344#, 32);
mem(1036) := To_stdlogicvector(16#44332211#, 32);
mem(1040) := To_stdlogicvector(16#55667788#, 32);
mem(1044) := To_stdlogicvector(16#88776655#, 32);
mem(1048) := To_stdlogicvector(16#99AABBCC#, 32);
mem(1052) := To_stdlogicvector(16#CCBBAA99#, 32);
mem(1056) := To_stdlogicvector(16#DDEEFF00#, 32);
mem(1060) := To_stdlogicvector(16#00FFEEDD#, 32);
mem(1064) := To_stdlogicvector(16#00011122#, 32);
mem(1068) := To_stdlogicvector(16#33344455#, 32);
mem(1072) := To_stdlogicvector(16#66677788#, 32);
mem(1076) := To_stdlogicvector(16#999AAABB#, 32);
mem(1080) := To_stdlogicvector(16#CCCDDDEE#, 32);
mem(1084) := To_stdlogicvector(16#FFF00011#, 32);
mem(1088) := To_stdlogicvector(16#00000000#, 32);
mem(1092) := To_stdlogicvector(16#00000000#, 32);
mem(1096) := To_stdlogicvector(16#00000000#, 32);
mem(1100) := To_stdlogicvector(16#00000000#, 32);
mem(1104) := To_stdlogicvector(16#00000000#, 32);
mem(1280) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1284) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1288) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1292) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1296) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1300) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1304) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1308) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1312) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1316) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1320) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1324) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1328) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1332) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1336) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1340) := To_stdlogicvector(16#DEADDEAD#, 32);
mem(1344) := To_stdlogicvector(16#00000000#, 32);
mem(1348) := To_stdlogicvector(16#00000000#, 32);
mem(1352) := To_stdlogicvector(16#00000000#, 32);
mem(1356) := To_stdlogicvector(16#00000000#, 32);
mem(1360) := To_stdlogicvector(16#00000000#, 32);
mem(1792) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1796) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1800) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1804) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1808) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1812) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1816) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1820) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1824) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1828) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1832) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1836) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1840) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1844) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1848) := To_stdlogicvector(16#DEADBEEF#, 32);
mem(1852) := To_stdlogicvector(16#DEADBEEF#, 32);

-- Stop.

		MemResp_H <= '0';
	else
              
		IF ((int_address >= 0) and (int_address <= 2048)) THEN
			IF (rising_edge(MemRead) and MemWrite = '0') THEN
				DataFromMem(31 downto 0) <= mem(int_address) after 43 ns;
                                DataFromMem(63 downto 32) <= mem(int_address+4) after 43 ns;
                                DataFromMem(95 downto 64) <= mem(int_address+8) after 43 ns;            
                                DataFromMem(127 downto 96) <= mem(int_address+12) after 43 ns;

                                MemResp_H <=  '0' after 1 ns, '1' after 43 ns, '0' after 60 ns;

                                ASSERT false
                                REPORT "Memory Read"
                                SEVERITY note;

                        ELSIF (rising_edge(MemWrite) and MemRead = '0') THEN
                                mem(int_address) := WBData(31 downto 0);
                                mem(int_address+4) := WBData(63 downto 32);
                                mem(int_address+8) := WBData(95 downto 64);
                                mem(int_address+12) := WBData(127 downto 96);

                                MemResp_H <=  '0' after 1 ns, '1' after 43 ns, '0' after 60 ns ;

                                ASSERT false 
                                REPORT "Memory Write"
                                SEVERITY note;

                        END IF;
                ELSE
			ASSERT false
			REPORT "Invalid address"
			SEVERITY warning;
		END IF;
        END IF;
                     
   END PROCESS vhdl_ext_data_mem;
END spec ;