ECE312 MP2 of Jason Wells

ECE312 MP2: VLSI datapath layout

The second MP of ECE325 involved the design and layout of a 4-bit microprocessor datapath based on a subset of the AMD 2901 instruction set. The third MP covered auto-generating a controlpath for this microprocessor. The transistor schematics for each functional block were provided, and from that I designed the transistor layout and interconnect via a sticks diagram on a per block basis. Next I used Mentor Graphics' IC Station to layout each functional block in the order as they appear below.

KEY
= active area (aa)
= contact (connects metal1 and aa)
= first of two metal layers
= second of two metal layers
= nplus region
= pplus region
= via (connects metal1 and metal2)
Here is shading key indicated in the following layouts. Process design rules set standards for the minimum size of overlap or separation between interacting layers. Process requirements also stipulated substrate contacts, and double width for PMOS transistors to match drive capability.

The "func" cell was the first cell I had created. Its purpose was to create propagate and generate signals (carried to the carry cell in the bottom metal2 tracks) as selected by the control signals, "X0-4", for a single bit slice. The "R" and "S" signals are the outputs from the operand select muxes and are the data bits on which the logic operations are performed. To save cell width nmos precharge-clear logic was used so that only thinner nmos transistors were needed In retrospect I realize that I could have reduced the cell width if I had not have chosen such a ridged intercell connection routing scheme.
This cell is used to calculate the value ("F") of the selected logic operation between the carry in ("Ci-1") and propagate ("P") values. For timing reasons "F" could not be precharged so cmos logic design was necessary.
The carry cell combines the propagate ("P) and generate ("G") values to produce a carry value which it will send to the next cell as "Ci-1". The important feature is its up/down direction option which allows cells to be flipped about the horizontal to allow overlap in "ground" and "VDD" tracks between bitslices of the microprocessor.
The above blocks combine to form a bitslice of the ALU as specified in the below schematic. The ALU block also includes simple precharge transistor and inverter functional blocks which are not show.
Here is the operand select cell which is used twice; once as a first register output/data in mux, and also as a second register output/zero mux.
Here is an instance of a single SRAM bit which can be selected to output to either the "Ai" or "Bi" tracks and read in from "RAMi".
Then four rams cells are combined to form a 4 register file (regfile) bitslice. "Ai" and "Bi" tracks are also precharged for nmos precharge-clear logic.
The AMD2901 also has the ability to do a prelogic shift. This shifter cell can pass the values retrieved from the regfile up a bitslice and down a bitslice. The circuitry for this is simply four transmission gates.
Here all the above cells are combined to form a single bitslice as illustrated in this schematic: The microprocessor uses a non-overlapping two clock system: "Phi1", during which operands are fetched, and "Phi2", during which they are evaluated.
The 1 bit slices are then cloned and alternately flipped about the horizontal so that power tracks may overlap. The schematic below shows inter-bitslice connections.

Each cell after layout was checked with Mentor Graphics' IC process rules checker and Logic Verification System (LVS). The LVS system ensure correlation between the VLSI design and the provided schematic. Simulations were run on both the 1bit ALU and 4bit microprocessor level using Mentor Graphics' QuickSim. Lastly I printed all the layouts and turned in a report including some design concept discussion.