--
-- Component : sexer
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 17, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- This component is a sign extender/zero extender. It handles converting
-- all immediate data into a 32 bit form which can be handled by the ALU.
-- This component was previously implemented as a splice, since it is
-- merely bit assignment, but has been placed in a transform of 0 delay
-- for data flow diagram simplification. 
ARCHITECTURE spec OF sexer IS
BEGIN

   -------------------------------------------------------------------
   vhdl_sexer : PROCESS (Imm)
   -------------------------------------------------------------------
   BEGIN
      if (imm(15) = '0') then
        SEx  <= "0000000000000000" & Imm;
        SEx2 <= "00000000000000" & Imm & "00";
      else
        SEx  <= "1111111111111111" & Imm;
        SEx2 <= "11111111111111" & Imm & "00";
      end if;
      Zex <= "0000000000000000" & Imm;
   END PROCESS vhdl_sexer ;
END spec ;

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