--
-- Component : registers
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- The register file will always output the contents of registers 
-- rs and rt on rout1 and rout2 respectively. In addition it will
-- write the dout data to the register selected by rout.
ARCHITECTURE spec OF registers IS
  type rammemory is array (31 downto 0) of mips_word;
  signal ram : rammemory;       
BEGIN 
  -------------------------------------------------------------------
  vhdl_regfile_read : PROCESS (ram, rs, rt)
  variable raddr1 : integer range 0 to 31;
  variable raddr2 : integer range 0 to 31;
  begin
    -- Read regfile Process.
    -- convert addresses to integers to use as an index into the array.
    raddr1 := to_Integer("000" & rs,0);
    raddr2 := to_Integer("000" & rt,0);
    ROut1 <= ram(raddr1) after 8 ns;
    ROut2 <= ram(raddr2) after 8 ns;
    DATAOUT <= ram(raddr2) after 8 ns;
  end process vhdl_regfile_read;

  -------------------------------------------------------------------
  vhdl_regfile_write: process(CLK, ROut, DOut, RegWrite_H)
  variable waddr : integer range 0 to 31;
  begin
    -- convert address to integer
    waddr := to_Integer("000" & ROut,0);
    if (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
      if (RegWrite_H = '1') then
        ram(waddr) <= DOut;
      end if;
    end if;
    ram(0) <= to_stdlogicvector(0,32);
  end process vhdl_regfile_write;

END spec ;

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