Instruction | Cycles | Frequency | CPI Fraction |
---|---|---|---|

r-type | 5 | 30% | 1.50 |

i-type | 5 | 15% | 0.75 |

beq, bne | 6* | 12% | 0.72 |

j | 6 | 4% | 0.24 |

jal | 6 | 2% | 0.12 |

jr | 6 | 2% | 0.12 |

lui | 5 | 5% | 0.25 |

lw | 8 | 20% | 1.60 |

sw | 7 | 10% | 0.70 |

CPI = |
6.00 |

* BEQ and BNE instructions take only 5 cycles when the branch is not taken and 7 cycles when the branch is taken. For the CPI calculation I assumed that the branch would be taken in half the instances producing an average cycle time of 6.

To calculate the CPI I assumed that all memory
access took one cycle. In retrospect some of the
cycles (such as the Compare state for branching) could
have been implemented in hardware or VHDL inside the
datapath. This would reduce the CPI but for accurate
simulation, the added logic would increase the delay
and thus lengthen the minimum cycle time.

Component | Delay |
---|---|

ALU | 15 ns |

ALU Control | 5 ns |

Register File | 8 ns |

Registers | 4 ns |

Multiplexors | 2 ns |

The critical path for my microprocessor is the fetch instruction. According to the above delays given for these components, the fetch will require 4 ns for the PC register output to become stable and 2 ns for this to propagate through the ALU select muxes. Thus the correct PC value will not reach the ALU for 6 ns. The ALU control outputs the correct value in parallel after 5 ns, so all ALU inputs are not stable until 6 ns. The ALU then takes 15 ns to compute the correct value, so that result is available at 6 ns + 15 ns = 21 ns into the cycle. Finally this value must propagate through the final PC write mux, an additional 2 ns, so that the PC can be written the next cycle. Thus the minimum cycle time must be greater than 23, thus I chose 24 as the minimum cycle time.