--
-- Component : pc_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Selects which will be writen to the PC: 
--   the ALU Output (for relative jumps),
--   the first register output (for jump register instructions),
--   the jump address,
--   the PC source (for inderect jumping), or
--   the target (for branch instructions).
ARCHITECTURE spec OF pc_mux IS
BEGIN
	-------------------------------------------------------------------
	vhdl_pc_mux : PROCESS (ALUOut, ROUT1, JAddr, PCSource, TOut)
	-------------------------------------------------------------------
		variable state : std_logic_vector(31 downto 0);
	BEGIN
		case PCSource is
			when "00" =>
				state := ALUOut;
			when "01" =>
				state := TOut;
			when "10" =>
				state := JAddr;
			when "11" =>
				state := ROUT1;
			when others =>
				state := (OTHERS => 'X');
		end case;

		PCin <= state after 2 ns;
	END PROCESS vhdl_pc_mux ;
END spec ;


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