--
-- Component : pc
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Holds the address of the next instruction.
ARCHITECTURE spec OF pc IS
   SIGNAL pre_Q : std_logic_vector(31 downto 0);
BEGIN

   -------------------------------------------------------------------
   vhdl_pc : PROCESS (PCIn, PCWrite_H, RESET_L, CLK)
   -------------------------------------------------------------------
   BEGIN
      IF ( RESET_L = '0' ) THEN
			pre_Q <= (OTHERS => '0');
      ELSIF (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0' ) THEN
			if (PCWrite_H = '1') then
				pre_Q <= PCIn;
         end if;
      END IF;
   END PROCESS vhdl_pc ;

   PCOut <= pre_Q after 4 ns;
END spec ;


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