The goal of this machine problem was to implement a hardwired microprocessor which would execute a subset of the MIPS instruction set including jump, immediate and register type instructions. The processor datapath was designed as a dataflow diagram of VHDL structures and the control unit was implemented as a Moore machine. Interface to a asynchronous memory unit was controlled via read/write handshaking.
This design was based on the one given in Patterson & Hennessy: Computer Organization and Design. The design was expanded to include immediate data instruction types, and interface with asynchronous memory. The control unit was also optimized to achieve a minimal average cycles per instruction (CPI) count.
The microprocessor was designed and compiled in Mentor Graphic's System Architect and verified by QuickHDL . Code was written to test each of the processor's 19 instructions and compiled using a MIPS assembler. The instructions were then placed in memory vectors which were fetched and executed by the microprocessor.
The following pages contain: dataflow and state diagrams for my
microprocessor, VHDL code, performance analysis, simulation test code
and result listings, and wave traces of three example instructions.
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