-- Component : memory
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 22, 97
--
-- sensitivity_attr :: 'transaction
-- Source views :-
-- $ECE_312_MP2/mips_types/types
-- 
--  This is the asynchronous memory unit which holds the instruction
-- and data memory. Because this unit is asynchronous the processor
-- waits for it to assert a response signal (MMRESP_H) before 
-- continuing. 

ARCHITECTURE spec OF memory IS
BEGIN
   -------------------------------------------------------------------
   vhdl_memory : PROCESS (RESET_L,MMRead_L,MMWrite_L)
   -------------------------------------------------------------------
   TYPE memory_array IS array (0 to 2048) of mips_word;
		VARIABLE mem : memory_array;
		VARIABLE int_address : integer;
	VARIABLE temp : string(1 to 10);
	VARIABLE temp_int : integer;
		BEGIN
			int_address := to_integer('0' & ADDRESS(10 downto 0));
			IF RESET_L = '0' then
			MMResp_H <= '0';

-- Insert Memory vectors here
mem(0) := To_stdlogicvector(16#34022020#, 32);
mem(4) := To_stdlogicvector(16#00421820#, 32);
mem(8) := To_stdlogicvector(16#08000000#, 32);
-- Stop.

		ELSE
			IF ((int_address >= 0) and (int_address <= 2048)) THEN
      		IF (MMRead_L = '0' and MMWrite_L = '1') THEN
         		DATAIN <= mem(int_address) after 50 ns;
					MMResp_H <= '1' after 50 ns, '0' after 80 ns;
				ELSIF (MMWrite_L = '0' and MMRead_L = '1') THEN
					mem(int_address) := DATAOUT;
					MMResp_H <= '1' after 2 ns, '0' after 30 ns;
					ASSERT false
					REPORT "Memory Write"
					SEVERITY note;
				END IF;
			ELSE
				ASSERT false
				REPORT "Invalid address"
				SEVERITY warning;
			END IF;
   	END IF;

	END PROCESS vhdl_memory ;
END spec ;

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