--
-- Component : ir
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Holds the current instruction.
ARCHITECTURE spec OF ir IS
   SIGNAL pre_Q : mips_word;
BEGIN

   -------------------------------------------------------------------
   vhdl_ir : PROCESS (DATAIN, IRWrite_H, CLK)
   -------------------------------------------------------------------
   BEGIN
		IF (CLK'EVENT AND CLK = '1' AND CLK'LAST_VALUE = '0' ) THEN
			if (IRWrite_H = '1') then 
				pre_Q <= DATAIN;
         end if;
      END IF;    
   END PROCESS vhdl_ir ;

   IROut <= pre_Q after 4 ns;
END spec ;


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