--
-- Component : d_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Selects what data is writen to the registers.
ARCHITECTURE spec OF d_mux IS
BEGIN
	-------------------------------------------------------------------
	vhdl_d_mux : PROCESS (ALUOut, LUIIn, MemToReg, PCOut, DATAIN)
	-------------------------------------------------------------------
		variable state : std_logic_vector(31 downto 0);
	BEGIN
		case MemToReg is
			when "00" =>
				state := ALUOut;
			when "01" =>
				state := PCOut;
			when "10" =>
				state := DATAIN;
			when "11" =>
				state := LUIIn;
			when others =>
				state := (OTHERS => 'X');
		end case;

		DOut <= state after 2 ns;
	END PROCESS vhdl_d_mux ;
END spec ;


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