This is the Moore state machine controller for my processor. All instructions begin with the writing of the next PC in the WritePC state (top). This state performs the addition to increment the PC then proceeds to fetch the instruction at the current PC. Notice that the IRwrite signal cannot be set before the memory has responded, thus an extra fetch state must be added where no signals are asserted and the processor will wait for the asynchronous memory. The instruction is then decoded and a branch target is calculated in the controller lag time. The controller will then take the appropriate steps for instruction completion based on the operand (and function if the instruction is rtype). Notice that all branch instructions must have a wait state for the PC to properly load. Also there must be a wait state for all memory reads, but memory writes occur quickly enough that no extra state is needed.


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