--
-- Component : b_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Selects the second alu input.
ARCHITECTURE spec OF b_mux IS
BEGIN

   -------------------------------------------------------------------
   vhdl_b_mux : PROCESS (ALUSelB, ROUT2, SEx, SEx2, ZEx)
   -------------------------------------------------------------------
   	variable state : std_logic_vector(31 downto 0);
   BEGIN
 		case ALUSelB is
			when "000" =>
         	state := ROUT2;
         when "001" =>
            state := to_stdlogicvector(4,32);
         when "010" =>
            state := SEx;
         when "011" =>
            state := SEx2;
         when "100" =>
            state := ZEx;
	      when others =>
 				state := (OTHERS => 'X');
		end case;

		inB <= state after 2 ns;
   END PROCESS vhdl_b_mux ;
END spec ;


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