--
-- Component : alu
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- This alu preforms 32 bit addition, subtraction, logical or, logical and,
-- logical shifts and a set-on-less-than. It also outputs a zero signal for
-- comparison checking.
ARCHITECTURE spec OF alu IS
BEGIN
   -------------------------------------------------------------------
   vhdl_alu : PROCESS (ALUCtrl, inA, inB)
   -------------------------------------------------------------------
     	variable result : mips_word;
		variable temp : mips_word;
		variable sha : integer range 0 to 31;
   BEGIN
		case ALUCtrl is 
			when aADD =>
				result := inA + inB;
			when aSUB =>
				result := inA - inB;
			when aAND =>
				result := inA and inB;
			when aOR  =>
				result := inA or inB;
			when aSLL =>
				sha := to_integer(inA(4 downto 0),0);
				result := inB sll sha;
			when aSRL =>
				sha := to_integer(inA(4 downto 0),0);
				result := inB srl sha;
			when aSLT =>
				temp := inA - inB;
				result := "0000000000000000000000000000000" & temp(31);
         when others =>
            result := (OTHERS => 'X');
		end case;
 
	   if (result = to_stdlogicvector(0,32)) then
			Zero <= '1' after 15 ns;
  		else
   	   Zero <= '0' after 15 ns;
   	end if;
  
   ALUOut <= result after 15 ns;

   END PROCESS vhdl_alu ;
END spec ;


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