--
-- Component : addr_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Selects indirect (all data memory access) or direct (fetching) addressing.
ARCHITECTURE spec OF addr_mux IS
BEGIN

   -------------------------------------------------------------------
   vhdl_addr_mux : PROCESS (ALUOut, IorD, PCOut)
   -------------------------------------------------------------------
		variable state : std_logic_vector(31 downto 0);
	BEGIN
		case IorD is
			when '0' =>
				state := PCOut;
			when '1' =>
				state := ALUOut;
			when others =>
				state := (OTHERS => 'X');
		end case;

		ADDRESS <= state after 2 ns;
	END PROCESS vhdl_addr_mux ;
END spec ;


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