--
-- Component : a_mux
--
-- Generated by System Architect version v8.5_2.2 by ja-wells on Feb 16, 97
--
-- sensitivity_attr :: 'transaction
-- 
-- Selects the first alu input.
ARCHITECTURE spec OF a_mux IS
BEGIN
   -------------------------------------------------------------------

   vhdl_a_mux : PROCESS (ALUSelA, PCOut, ROUT1, ShAmt)
   -------------------------------------------------------------------
		variable state : std_logic_vector(31 downto 0);
   BEGIN
   	case ALUSelA is
      	when "00" =>
          	state := PCOut;
         when "01" =>
            state := ROUT1;
         when "10" =>
            state := to_stdlogicvector(0,27) & ShAmt;
         when others =>
            state := (OTHERS => 'X');
         end case;

         inA <= state after 2 ns;
   END PROCESS vhdl_a_mux ;
END spec ;

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